1. Field of the Invention
The present invention relates to a layout method for voltage division resistors of a liquid crystal bias level generation circuit in a liquid crystal display (LCD) driver, and in particular, to a layout method for voltage division resistors in the case of employing a photolithographic system having manufacturing variations in the longitudinal direction of a layout area.
2. Description of the Related Art
In general, a conventional layout of voltage division resistors of a liquid crystal bias level generation circuit in a liquid crystal display (LCD) driver has been designed such that resistors R1, R2, R3, R4, and R5 are laid out in sequence from left to right as shown in FIG. 3 in the case where a resistance ratio of R1 to R5 is set at 1:1:(n−4):1:1(n represents the number of biases, assuming a value in the order of n=6˜13) as shown in the figure. That is, according to a conventional designing technique, as for R1, R2 portions of the voltage division resistors, each having an identical resistance value, a portion extending to a length L (pattern width: W) from the extreme left is designated the resistor R1, and another portion extending to a length L from R1 is designated the resistor R2. As for the resistor R3, a portion extending to a length L (n−4) from the back-end of R2 is designated the resistor R3, and the resistors R4, R5, extending to a length L from the back-end of R3, and R4, respectively, are laid out.
With the conventional technique of designing voltage division resistors, however, there has arisen a problem that, in the case of laying out the voltage division resistors by use of a photolithographic system having manufacturing variations in the longitudinal direction of a layout area, there result variations in accuracy of resistance value of the respective voltage division resistors, that is, in relative accuracy of divided voltage levels.
More specifically, if reduction in power consumption is attempted by decreasing current flowing through voltage division resistors in the case of the voltage division resistors being manufactured of polysilicon material from the viewpoint of layout efficiency, there is the need for setting a resistance value of the respective voltage division resistors to a high value. In such a case, assuming that polysilicon resistors are designed to have the minimum widths that are manufacturing limits, resistance values of the voltage division resistors should be designed to have relative values expressed by a ratio of 1:1:(n−4):1:1 at 1/n bias, however, in the case of employing the photolithographic system having the characteristic described above, there has arisen a case where while resistance width W of the resistor R3 disposed in the vicinity of the center in FIG. 3 is 0.70 μm, resistance width W of the resistor R5 at the extreme right is 0.65 μm, and resistance width W of the resistor R1 at the extreme left is 0.75 μm. Accordingly, if voltage is divided with the use of such voltage division resistors, a divided voltage ratio will be 0.93:0.95:(n−4):1.05:1.07, thus resulting in variations of divided voltages, so that there has arisen a problem that a specification as required can not be met.
It is therefore an object of the invention to provide a layout method for voltage division resistors, enabling variations in divided voltages to be controlled within required accuracy.